Adjustment of a clock duty cycle

ABSTRACT

Circuits for adjusting the duty cycle of a clock(s) signal include a negative feedback loop for applying an offset signal to the uncorrected clock signal(s). The offset signal, which corresponds to a duty cycle error of the corrected clock signal(s), adjusts the slicing level of the uncorrected clock signal(s) to cause the duty cycle error to converge toward a predetermined value, for example, zero. The techniques may be used to adjust the duty cycle error of differential clock signals as well as single-ended clock signals.

BACKGROUND

The present disclosure relates to adjustment of a clock duty cycle.

Clock signals may be used in electronic circuits to provide timinginformation. An important aspect of a clock signal in many applicationsis the clock duty cycle, which may be defined as the ratio of the timethe clock pulse is at a high level to the clock period. For example, aclock signal that is at the high level for one-half of the clock periodand the low level for one half the clock period has a 50% duty cycle.

A 50% duty cycle is desirable for many applications. For example, inclock-driven digital systems requiring high speed operation, both therising and falling edges of the clock signal may be used to increase thetotal number of operations. Such systems may require a 50% duty cycle tohelp prevent or reduce jitter and other timing related distortions. Insuch systems, the duty cycle may be critical to proper performance ofthe system. Unfortunately, the duty cycle of the clock signal may becomedistorted or degraded, for example, as a result of semiconductor processerrors. Other conditions also may cause the duty cycle to deviate fromthe desired value. Duty cycle correction circuits may be used to corrector adjust such distortions.

BRIEF DESCRPTION OF THE DRAWINGS

FIG. 1 is a diagram of a circuit for adjusting the duty cycle ofdifferential clock signals.

FIGS. 2(a) through 2(d) are examples of timing diagrams for FIG. 1.

FIG. 3 illustrates further details of the circuit of FIG. 1 according toone implementation.

FIG. 4 illustrates details of a charge pump that may be used in thecircuit of FIG. 1 according to one particular implementation.

FIG. 5 is a diagram of a circuit for adjusting the duty cycle of asingle-ended clock signal.

SUMMARY

Circuits for adjusting the duty cycle of a clock(s) signal include anegative feedback loop for applying an offset signal to the uncorrectedclock signal(s). The offset signal, which corresponds to a duty cycleerror of the corrected clock signal(s), adjusts the slicing level of theuncorrected clock signal(s) to cause the duty cycle error to convergetoward a predetermined value, for example, zero. The techniques may beused to adjust the duty cycle error of differential clock signals aswell as single-ended clock signals.

In various implementations, the feedback loop may include a charge pumpand an integrator to receive an output from the charge pump. A netcharge in the integrator may correspond to the duty cycle error. Adriver may be provided to amplify and clamp the values of the clocksignals after applying a DC offset signal to the uncorrected clocksignal(s).

Various implementations may include one or more of the followingadvantages. For example, the circuits may be used to correct a signalhaving an arbitrary duty cycle to a signal having the same frequencywith a 50% duty cycle. Use of an integrator in the feedback loop mayallow the gain to be sufficiently large to minimize or reduce the dutycycle error.

Other features and advantages will be readily apparent from thefollowing detailed description, the accompanying drawings and theclaims.

DETAILED DESCRIPTION

As shown in FIG. 1, a circuit 20 may be used to adjust the differentialduty cycle for a pair of clock signals (CN, CP). In particular, thecircuit 20 may be used to correct the differential duty cycle and causeit to converge toward 50%.

The circuit uses a negative feedback configuration that adds a DC offsetsignal (V_(OS)) to the uncorrected clock signals (CN, CP). The DC offsetvoltage (V_(OS)) may be added to the input clock signals using summers22, 24, to produce corrected clock signals, CN′ and CP′, respectively.

The corrected clock signals (CN′, CP′) are applied as inputs to a driver26 which forms part of the feedback loop. The output signals (OUTN,OUTP) from the driver 26 represent the clock signals with the correcteddifferential duty cycle. The driver may provide a high gain and mayclamp the maximum amplitude of the output clock signals at a fixed valueto prevent amplitude variation.

The feedback loop also includes a differential charge pump 28 andintegrator 30 which together produce an error voltage proportional tothe duty cycle error. The output clock signals from the driver 26 areapplied, respectively, to input terminals (UP, DN) of the charge pump.When the signal at the terminal UP is a high level signal and the signalat the terminal DN is a low level signal, the charge pump sources acurrent I_(UP) from one output (I) and sinks substantially the sameamount of current into the second output {overscore (I)}. Conversely,when the signal at the terminal input UP is a low level signal and thesignal at the terminal DN is a high level signal, the currents flow inthe opposite direction—in other words, the charge pump sources a currentI_(DN) from the output {overscore (I)} and sinks substantially the sameamount of current into the output I. The outputs of the charge pump areindicative of the instantaneous time difference between the high and lowstates of the clock signals. For example, if the duty cycle of the clocksignals were exactly 50%, the average net output of the charge pumpwould be about zero.

The current signals from the output terminals (I and {overscore (I)}) ofthe charge pump are applied as input signals to the integrator 30. Theintegrator may include capacitors (not shown in FIG. 1) which arecharged and discharged depending on the output currents from the chargepump 28. The net charge on the capacitors is proportional to theintegrated value of the deviation of the clock signals from apredetermined duty cycle, for example, a 50% duty cycle. The DC offsetvoltage (V_(OS)) corresponds to the net charge and represents the dutycycle error of the differential clock signal (CP′−CN′). For example, ifthe differential duty cycle were exactly 50%, then the DC offset voltage(V_(OS)) would be about zero volts. On the other hand, as the duty cycledeviates from 50%, the DC offset voltage will vary as well. Applying theDC offset voltage signal to the input clock signals CN, CP adjusts thezero crossing point, or slicing level, of the input clock signals sothat the differential duty cycle converges toward 50%.

FIG. 2(a) illustrate an example of a timing diagram in which it isassumed that the input clock signals have a duty cycle that deviatesfrom 50%. In that case, the duty cycle of the differential clock signal(CP−CN) also will deviate from 50%. The feedback loop causes the offsetvoltage V_(OS) to be applied to the input clock signals, effectivelyshifting the zero crossing (i.e., slicing level) of the clock signals,as illustrated in FIG. 2(b). Although each of the modified clock signals(CP′, CP′) has approximately a 50% duty cycle, the duty cycle of thedifferential clock signal (CP′−CP′) may still deviate from 50% as aresult of the amplitude variations in the modified clock signals. Thedriver 26 amplifies and clamps the modified clock signals to produce theoutput clock signals (OUTP, OUTN), as illustrated in FIG. 2(c). Theoutput clock signals have approximately a 50% duty cycle. Furthermore,as shown by FIG. 2(d), the differential clock signal, OUTP−OUTN, alsohas approximately a 50% duty cycle.

A particular implementation of the duty cycle correction circuit isshown in FIG. 3. In this implementation, the driver includes a pair ofsingle-ended drivers, such as complementary metal oxide semiconductor(CMOS) inverters 32, 34. The input clock signals (CP, CN) may beAC-coupled through the respective capacitors C_(C) to the CMOS inverterswhich drive external loads shown as a pair of capacitors C_(L). Theinput to each inverter is the sum of the offset voltage (V_(OS)) and thecorresponding uncorrected clock signal.

In other embodiments, the driver 26 may be implemented as a differentialamplifier.

The charge pump 28 may operate at the input clock rate. One specificimplementation of the charge pump is illustrated in FIG. 4 and includesa p-type MOS current source, an n-type MOS current sink, and CMOSswitches to direct the currents. Other types of charge pumps may be usedas well.

The integrator 30 may be implemented as a passive integrator includingone or more capacitors. Alternatively, as shown in FIG. 3, the feedbackloop may include an active integrator. In the implementation of FIG. 3,the active integrator 30 includes a differential operational amplifier38 and feedback capacitors C_(p), C_(n). The output clock signals (OUTP,OUTN) drive the charge pump 28, which charges and discharges thecapacitors C_(p), C_(n). The active integrator keeps the potentials ofthe output terminals of the charge pump substantially equal to oneanother. The charge pump output currents may, therefore, be independentof the duty cycle error, as well as the offset voltage (V_(OS)), therebyrelaxing requirements on the charge pump. The integrator outputs are fedback through a pair of resistors R_(F) to control the DC voltage acrossthe AC-coupling capacitors C_(C).

To ensure stability of the duty cycle correction loop, the values of thefeedback capacitors C_(p) and C_(n) in the integrator should be largeenough to provide sufficient phase margin.

In some applications, the input offset voltage (V_(offset)) of theoperational amplifier 38 may cause a small duty cycle error in theoutput. The error in the output is proportional to the input offsetvoltage and is inversely proportional to the slew rate (r) and period(T) of the input signal. For example, assuming that the rise and falltimes are one fourth the period—r·(T/4)=V_(DD)=1.2 volts—then an inputoffset voltage of 10 millivolts (mV) would result in an output dutycycle error or about only 0.4%.

Although the particular circuits described above are illustrated in thecontext of differential clock signals, the techniques may be used foradjusting the duty cycle of a single-ended clock signal as well. Asshown in FIG. 5, a negative feedback loop may be used to adjust the dutycycle of the single-ended clock signal CP and to cause it to convergetoward 50%. The amplified clock output signal (OUT) from the driver 26serves as the input to the UP terminal of the charge pump 28. The clockoutput signal (OUT) also may serve as the input to an inverter 40 whoseoutput is provided to the DN terminal of the charge pump. The outputcurrent from the terminal (I) of the charge pump serves as the input tothe integrator 30. The DC offset voltage at the output of the integratorrepresents the DC component of the clock signal (CP′) which, in turn,corresponds to the duty cycle error. Feeding the DC offset voltage backto the summer 24 causes the duty cycle to converge toward 50%.

The foregoing techniques may be used for clock signals at high or lowfrequencies, but may be particularly advantageous for frequencies of1.25 gigahertz (GHz) and higher. The techniques may be useful, forexample, in high-speed digital transmitters in which the output data isclocked by a double-edge-triggered (DET) flip-flop. The techniques maybe used in other systems as well.

Other implementations are within the scope of the claims.

1-18. (canceled)
 19. A method comprising: obtaining one or morecorrected clock signals based on one or more uncorrected clock signals;obtaining a DC offset signal corresponding to a duty cycle error of theone or more corrected clock signals; and adjusting a slicing level forthe one or more uncorrected clock signals based on the DC offset signal,wherein the adjusting includes adding the DC offset signal to the one ormore uncorrected clock signals.
 20. The method of claim 19 includingrepeating said obtaining one or more corrected clock signals, obtaininga DC offset signal and adjusting a slicing level, wherein adjusting theslicing level causes the duty cycle error to converge toward apredetermined value.
 21. The method of claim 20 wherein the duty cycleerror converges toward zero.
 22. The method of claim 21 wherein the dutycycle error is a differential duty cycle error for a pair of correctedclock signals.
 23. A method comprising: receiving an uncorrected clocksignal as an input to a negative feedback loop; producing an integratedcharge signal that is proportional to a clock duty cycle error;producing an offset voltage signal based on the integrated chargesignal; and adjusting a slicing level for the uncorrected clock signalbased on the offset voltage, wherein the adjusting includes adding theoffset voltage signal to the uncorrected clock signal.
 24. The method ofclaim 23 wherein adjusting the slicing level includes adding the offsetvoltage signal to the uncorrected clock signal.
 25. The method of claim24 including: amplifying a signal representing a sum of the uncorrectedclock signal and the offset signal; clamping the amplified signal; andproducing a corrected clock signal based on the clamped signal.
 26. Themethod of claim 25 wherein the integrated charge signal is proportionalto a duty cycle error of the corrected clock signal.
 27. The method ofclaim 25 including producing a corrected clock signal having a dutycycle that converges toward a predetermined value.
 28. The method ofclaim 25 including producing a corrected clock signal having a dutycycle that converges toward about 50%.
 29. The method of claim 25including repeatedly producing an offset voltage signal based on theintegrated charge signal and adjusting a slicing level for theuncorrected clock signal based on the offset voltage.
 30. The method ofclaim 25 wherein producing an integrated charge signal includesproducing a signal indicative of a time difference between high and lowstates of the clock signal, wherein the integrated charge signal isproportional to an integrated value of a deviation of the clock signalfrom a predetermined duty cycle.
 31. A method comprising: receiving aplurality of uncorrected clock signals as input to a negative feedbackloop; producing a net integrated charge that is proportional to a dutycycle error; producing an offset voltage signal based on the netintegrated charge; and adjusting a slicing level for the uncorrectedclock signals based on the offset voltage, wherein the adjustingincludes adding the offset voltage signal to the uncorrected clocksignals.
 32. The method of claim 31 wherein adjusting the slicing levelincludes adding the offset voltage signal to the uncorrected clocksignals.
 33. The method of claim 32 including: amplifying signals eachof which represents, respectively, a sum of one of the uncorrected clocksignals and the offset signal; clamping the amplified signals; andproducing corrected clock signals based on the clamped signals.
 34. Themethod of claim 33 wherein the net integrated charge signal isproportional to a differential duty cycle error of the corrected clocksignals.
 35. The method of claim 33 including producing corrected clocksignals having a differential duty cycle that converges toward apredetermined value.
 36. The method of claim 33 including producingcorrected clock signals having a differential duty cycle that convergestoward about 50%.
 37. The method of claim 33 including repeatedlyproducing an offset voltage signal based on the net integrated chargeand adjusting a slicing level for the uncorrected clock signals based onthe offset voltage.
 38. The method of claim 33 wherein producing anintegrated charge signal includes producing a signal indicative of atime difference between high and low states of the clock signal, whereinthe integrated charge signal is proportional to an integrated value of adeviation of the clock signal from a predetermined duty cycle.